The wire-lengths, I mean ...

XILINX even has a flag that you can set in their "IMPACT" software that programs CPLD's and FPGA's using a programmer of this sort, albeit with JTAG protocol. However, I've had pretty good luck (not one failure in well over a decade) with "fly-wired" adapters ranging in wire-length (the last foot) of up to 50 cm at the end of a 3-meter-long parallel port cable. I doubt that clock corruption, ringing, reflections, or other bugaboos are that large a factor.

Altera uses similar cabling, and I've had no apparentl problems with their software either, though they don't provide a "slow-down" flag.

Clearly, these two "biggies" in the PLD market have figured out how to manage the cabling issues. If ATMEL hasn't managed it, that should surprise no one. If anyone else has similar problems to the ATMEL problems, well, their marketing department probably drove them to it.

Because I've never had troubles with programming, irespective of the cable length I've used, I've never had cause to examine the signal quality with a 'scope, so it's anybody's guess what's really going on. I may, so far, simply have been lucky!

RE