| ??? 08/07/07 19:34 Read: times |
#142897 - State Machine Responding to: ???'s previous message |
Part of the opcode specifies the source and destination for data transfers, and part of the instruction programs the step count into the state machine that makes it all happen.
RE |
| Topic | Author | Date |
| decoding | 01/01/70 00:00 | |
| It's implicit | 01/01/70 00:00 | |
| design | 01/01/70 00:00 | |
| A little ambitious? | 01/01/70 00:00 | |
| First stop - instruction set | 01/01/70 00:00 | |
| no intelligence | 01/01/70 00:00 | |
| Back to basics! | 01/01/70 00:00 | |
| Instruction decoding | 01/01/70 00:00 | |
| decoder unit | 01/01/70 00:00 | |
| State Machine | 01/01/70 00:00 | |
| more detail | 01/01/70 00:00 | |
| IF you've learned the "basics" of FPGA design ... | 01/01/70 00:00 | |
| Decoding | 01/01/70 00:00 | |
| in a traditionally anthropomorphic metaphor? | 01/01/70 00:00 | |
| My favourite anthropomorphic metaphor... | 01/01/70 00:00 | |
| My favorite ... | 01/01/70 00:00 | |
| Blither | 01/01/70 00:00 | |
| re: blither | 01/01/70 00:00 | |
| I always think that a blithering idiot.. | 01/01/70 00:00 | |
| anthropomorphic metaphor | 01/01/70 00:00 | |
| The same way ... | 01/01/70 00:00 | |
| Dictionary | 01/01/70 00:00 | |
If anyone is still listening... | 01/01/70 00:00 |