| ??? 10/05/07 17:22 Read: times |
#145490 - you are right Responding to: ???'s previous message |
No I don't have emulator.
And you are right ! :) Just explain me the reason of what you told in the quote below. I've been using CPU for 20 years now and still don't see why we could not re-enter an ISR. And worse, I did it lots of times. Erik Malund said:
Whatever means you use, if Atmel has not (as usual) screwed up, this will not be true. An interrupt interrupting itself would make total havoc in countless designs. I would not touch an Atmel with a ten foot pole, but maybe someone that does not have this adversity could confirm "you MUST be wrong" You have a strange understanding of the CPU design. Nobody would design a core tracking the origin of every exception (IT is an exception). We only care of priority levels. There are plenty of reasons to re-enter an ISR. Such implementation is cheaper in gates and more flexible. And just a detail: a customer would laugh at me if I had presented to him a CPU core which hangs up when an exception is re-entered. It would be a bug. |
| Topic | Author | Date |
| I tested changing prio level from the IT, it works | 01/01/70 00:00 | |
| you MUST be wrong | 01/01/70 00:00 | |
| For Erik | 01/01/70 00:00 | |
| redefine test | 01/01/70 00:00 | |
| what??? and comments | 01/01/70 00:00 | |
| what | 01/01/70 00:00 | |
| IT in derivatives | 01/01/70 00:00 | |
| Stored edges | 01/01/70 00:00 | |
| I'm still certain | 01/01/70 00:00 | |
| I don't see well what you mean. | 01/01/70 00:00 | |
| how about an answer | 01/01/70 00:00 | |
| you are right | 01/01/70 00:00 | |
just read \"the bible\" | 01/01/70 00:00 |