Just explain me the reason of what you told in the quote below

just read "the bible".

You have a strange understanding of the CPU design.
whatever understanding I have of CPU design is long forgotten. I have not designed a CPU since ~1990, only used them since then.

There are plenty of reasons to re-enter an ISR.
Give me just one, that would not screw the whole thing up.

a customer would laugh at me if I had presented to him a CPU core which hangs up when an exception is re-entered. It would be a bug.
The '51, and all CPUs I know of, do not hang up if an interrupt is requsted while same is being processed, they just hold off execution till the ISR has completed.
Strange customer. You use 'exception' not 'interrupr' and, taking as an example, a very common exception: power fail. If you are processing power fail why on earth would you want to be told again.

If, indeed, you mean interrupt, just visualize a high speed charater transfer you have just started processing character n, then you get reinterrupted by character n+1 which you, thus, process before character n, that would be a ufck up.

Erik

PS you made some comments of the difficulty with KISS, I have yet to see an ISR I could not make faster.

PPS here are the links to "the bible"
Chapter 1 - 80C51 Family Architecture:
http://www.nxp.com/acrobat_d...ARCH_1.pdf

Chapter 2 - 80C51 Family Programmer’s Guide and Instruction Set:
http://www.nxp.com/acrobat_d...UIDE_1.pdf

Chapter 3 - 80C51 Family Hardware Description:
http://www.nxp.com/acrobat_d...WARE_1.pdf