| ??? 11/29/07 13:41 Read: times |
#147558 - memory mapped antique - beware ... Responding to: ???'s previous message |
of the big bad .. eh make absolutely sure that you check the datasheet for the actual (not from a datasheetcollector but from the manufacturer) antique you use and the datasheet for the uC at the clock rate and division (6/12) you run at and verify you run within the timings.
Yes, i have basic C code to address P3.7 (port 3 pin 7). and Memory mapped! That is contradictory, if the antique is memory mapped you access it by mov @dptr (XDATA in C) and that generates the !WR and !RD signals on p3 6 and 7. Erik |
| Topic | Author | Date |
| Q for Richard Erlacher | 01/01/70 00:00 | |
| Is only Richard allowed to reply, then? | 01/01/70 00:00 | |
| Not afraid! | 01/01/70 00:00 | |
| How is the 8255 connected? | 01/01/70 00:00 | |
| I'll just go look at the user page. | 01/01/70 00:00 | |
| You mean this? | 01/01/70 00:00 | |
| XDATA | 01/01/70 00:00 | |
| Memory mapped! | 01/01/70 00:00 | |
| Sarcasm not in short supply! | 01/01/70 00:00 | |
| questions with questions | 01/01/70 00:00 | |
| I am just a lowly noob... | 01/01/70 00:00 | |
| memory mapped antique - beware ... | 01/01/70 00:00 | |
| if we do the usual guesswork... | 01/01/70 00:00 | |
| Spanish | 01/01/70 00:00 | |
| Your question is vague and confusing! | 01/01/70 00:00 | |
| Thankyou Richard and Andy. | 01/01/70 00:00 | |
No worries, mate! | 01/01/70 00:00 |