First of all, when using the memory-mapped approach to interfacing this old war-horse, you must be certain that you have an 8255 that's fast enough, and an 805x-clone that's slow enough that the resulting external data memory bus bus will meet the timing requirements. Some MCU's, and I don't know about this particular one, allow you to set the timing of the external memory bus cycle without altering the remainder of the MCU's timing.

Pin 3.7 is not defined as an I/O if you are using an external data memory bus, as it is the nRD signal. When using the external data memory bus, you lose the pins that provide the nRD, nWR, and the P0 and P2 pins for I/O. It's a choice you have to make before using that approach. Using two ports (P0 and P2) plus a couple of P3 bits to create the external memory bus is not very efficient use of on-chip resources if you just need the three ports on the 8255. However, if you need external memory bus anyway, you gain the extra I/O at very little cost.

If you want to know what the individual bit addresses on the 8255 will be after expansion, you have to read the datasheet, keeping in mind what the base address of the 8255 is, and then write your code in a way that enables you to address each bit individually, and control it as such, if that's what you need to do.

If you need to retain control of the I/O's on the MCU, then I'd suggest you use the port-mapped approach, which enables you to use all the MCU pins however you like, with the exception of the one dedicated to the nCS on the 8255. This gives you more freedom with respect to timing, but also places the burden for maintaining the correct timing on your code. Do do, of course, have to be aware of what each I/O is doing at any given time so you don't inadvertently cause undesired things to happen. Again, using many pins to attach a single 8255 is not terribly efficient use of the MCU pins, but adding a second or third one to expand the I/O requires just one more bit as the nCS of each 8255.

RE