Email: Password: Remember Me | Create Account (Free)

Back to Subject List

Old thread has been locked -- no new posts accepted in this thread
???
04/26/08 09:24
Read: times


 		 #154005 - Tristate (pedant mode, again)
Responding to: ???'s previous message
P.a.s.r. Naren said:
If you see the datasheets of 2 Wire interface EEPROMs, you can find that SDA line is open drain(which works as tristate)

Again, "Tristate" is usually taken to mean something distinct from "Open-Drain" (or "open-collector") - see http://www.8052.com/forum/read.phtml?id=153948

Literally speaking, the term Tri-state must mean that a pin has three states:
1. Actively driving high;
2. Actively driving low;
3. High-impedance.

But an Open-Drain pin has only two states:
1. Actively pulling low;
2. High-impedance.






List of 33 messages in thread
TopicAuthorDate
about port 0 0f 8051mc            01/01/70 00:00      
   already answered            01/01/70 00:00      
      P0 pullups            01/01/70 00:00      
         Tristate (pedant mode)            01/01/70 00:00      
         This thread turns to helter-skelter            01/01/70 00:00      
         I never heard of that            01/01/70 00:00      
            I never heard of that ?            01/01/70 00:00      
            I never heard of that ?            01/01/70 00:00      
               Tristate (pedant mode, again)            01/01/70 00:00      
                  three states            01/01/70 00:00      
                     not at all confusing            01/01/70 00:00      
               confusing open drain/collector with tristate ...            01/01/70 00:00      
                  Not quite true            01/01/70 00:00      
                     much 'can' be done            01/01/70 00:00      
   read the datasheet ... it is "open-drain"            01/01/70 00:00      
      advantage            01/01/70 00:00      
         that it is not clogged            01/01/70 00:00      
            or a wire-or-ed output            01/01/70 00:00      
               ????            01/01/70 00:00      
         How would you realize an input /output topology?            01/01/70 00:00      
            why            01/01/70 00:00      
               this is the diagram of the "inside" of chip            01/01/70 00:00      
            please comment            01/01/70 00:00      
               1) Maybe, 2) False, 3) False            01/01/70 00:00      
               FAQ            01/01/70 00:00      
               Have you read at all what I wrote??            01/01/70 00:00      
   Port 0            01/01/70 00:00      
      Hhm, still no answer??            01/01/70 00:00      
         This doc explained everything            01/01/70 00:00      
            it should be the first reference!            01/01/70 00:00      
      P0.1            01/01/70 00:00      
         start a new thread            01/01/70 00:00      
         yes to both - it\'s \"bible time\"            01/01/70 00:00      

Back to Subject List