for me anyway........at 3.3V that is 66mV of possible error in either direction. I should have caught that in the datasheet, but at least I know that I'm at the limits of the LPC936.

So for the original poster and myself, in simplest terms, we must allow for ~66mV (3.3V rail)of noise margin before a shift occurs in the ADC if its valid or invalid.....as well as ensure clean rail voltages so that the noise is not additive to the incoming voltage.

That is one of the tradeoffs of having onboard devices, you're at the mercy of the manufacture for those specs.....if something with better immuninity is needed, then a standalone ADC would be in order it seems.

Either way, it looks like we have a valid solution, and now need to code with some noise margin limits.

Thanks Richard....it's clear now and exactly what I'm seeing on the bench. I hope this also helps the original poster as well.