??? 06/25/08 16:50 Read: times |
#156206 - Boring discussion Responding to: ???'s previous message |
Your talking about negative or and positive and is not very helpful and surely no answer to my question.
The glue logic of my boards usually consists of a 74HCT00. One gate is used to put /PSEN and /RD together, another one to invert this and achive a signal I call /OE (wich is connected to the /OE pin all memory ICs) and a third one to invert A15. /CS of the Flash is connected to A15, /CS of the RAM to /A15. All /WR pins are simply connected together. (Harvard architecture vs. von Neumann architecture) The forth gate of the '00 is usually not used in my applications. It all works fine in this way, considering that the memory timing is chanced - you have to run the micro with a lower quartz frequency. Wheter /PSEN is a push-pull output or not, it would be short circuit to ground, setting the corresponding port pin of /RD (is it P3.7?) to low. Besides this, a code fetch can never be done at the same time, a data fetch is done, so it might be possible to put this two together without a fatal design error. |
Topic | Author | Date |
Connecting /PSEN and /RD directly together | 01/01/70 00:00 | |
'guess' is not a design criteria | 01/01/70 00:00 | |
Lots of boards use an AND gate. | 01/01/70 00:00 | |
nope | 01/01/70 00:00 | |
I beg your pardon ... | 01/01/70 00:00 | |
unadulterated male cow manure | 01/01/70 00:00 | |
Definition is correct | 01/01/70 00:00 | |
go back to your 1st-year logic text | 01/01/70 00:00 | |
use your own link and find out you are wrong | 01/01/70 00:00 | |
Erik, perhaps you just need to learn to read | 01/01/70 00:00 | |
I\'m not | 01/01/70 00:00 | |
Erik, all logic is positive | 01/01/70 00:00 | |
ask Mr Boole | 01/01/70 00:00 | |
Input and Output is negative logic | 01/01/70 00:00 | |
re;negative OR | 01/01/70 00:00 | |
nope | 01/01/70 00:00 | |
Boring discussion | 01/01/70 00:00 | |
WRONG!!! | 01/01/70 00:00 | |
one resistor? | 01/01/70 00:00 | |
Whats the point ? | 01/01/70 00:00 | |
You are right. | 01/01/70 00:00 | |
not necessarily "non-dangerous" | 01/01/70 00:00 | |
delayed with sure, but non overcurrent-ed![]() | 01/01/70 00:00 |