| ??? 06/27/08 05:18 Read: times |
#156235 - delayed with sure, but non overcurrent-ed Responding to: ???'s previous message |
| Topic | Author | Date |
| Connecting /PSEN and /RD directly together | 01/01/70 00:00 | |
| 'guess' is not a design criteria | 01/01/70 00:00 | |
| Lots of boards use an AND gate. | 01/01/70 00:00 | |
| nope | 01/01/70 00:00 | |
| I beg your pardon ... | 01/01/70 00:00 | |
| unadulterated male cow manure | 01/01/70 00:00 | |
| Definition is correct | 01/01/70 00:00 | |
| go back to your 1st-year logic text | 01/01/70 00:00 | |
| use your own link and find out you are wrong | 01/01/70 00:00 | |
| Erik, perhaps you just need to learn to read | 01/01/70 00:00 | |
| I\'m not | 01/01/70 00:00 | |
| Erik, all logic is positive | 01/01/70 00:00 | |
| ask Mr Boole | 01/01/70 00:00 | |
| Input and Output is negative logic | 01/01/70 00:00 | |
| re;negative OR | 01/01/70 00:00 | |
| nope | 01/01/70 00:00 | |
| Boring discussion | 01/01/70 00:00 | |
| WRONG!!! | 01/01/70 00:00 | |
| one resistor? | 01/01/70 00:00 | |
| Whats the point ? | 01/01/70 00:00 | |
| You are right. | 01/01/70 00:00 | |
| not necessarily "non-dangerous" | 01/01/70 00:00 | |
delayed with sure, but non overcurrent-ed | 01/01/70 00:00 |