Yes, the off-chip RAM high-address-byte appears on P2, on most chips (not necessarily on SiLabs) but it's really addressed by DPTR and not by P2. You can, of course, write a byte to P2 and use it as the high address using R0 or R1 to provide the low byte. DPTR is faster, though.

It's getting messy, as 805x architecture expansion continues, and we need to be very precise with nomenclature in order to avoid mixing up details such as where the memory lives, physically, with how it's addressed.

SiLabs provides 8 KB of what's addressable as external memory. Maxim/Dallas provides that 1 KB buffer, and, IIRC, some NXP parts provide half-a-kB of on-chip data memory of some sort, but I've got no idea how it's addressed. I suspect NXP's is split up in some peculiar way ...

The trick is to keep things straight in our collective understanding, so that when we refer to a given thing, it's clear to everybody what is meant.

RE