Yes, and I'd be really interested in what happens when you put on an external 32KB of SRAM and then address the on-chip 8KB and the off-chip 32 KB as though they were the same block. .
you can configure it external only or 'mixed'. If mixed the first 8k are directed internally and the rest is directed externally the transition is seamless except for the external access probably taking more time (again configurable, but typical RAMs will require you to slow the external access down compared to the internal).

I'd also be interested in knowing what happens when you access that on-chip 8KB block (on the 'F12x) using a MOVX A,@Ri instruction rather than with DPTR, which specifies the upper address
there is a SFR for the upper address.

Erik