| ??? 01/17/02 01:03 Read: times |
#18808 - RE: 8 bit address/data bus and memory I/ |
First of all excuse my error, I am using ALE to latch the address. I'm using the RD and WR 'nored' with the address decode (Done with GAL16V8) to enable the HCTL.
By 16-bit vs 8-bit I mean: Most of the examples you see use address lines A8-A15 as part of the address decode or chip enable. I would like to keep P2 open, so I am just using A0-A7 to decode and enable I/O. I have read that you can do this, but haven't really seen any examples. What I have seems to be working but has a little glitch somewhere. I think that I am getting a zero value instead of the expected 2 or 3 counts from the HCTL. This would explain why the rollers feed more than they should and it's not always the same. The fact that I added a small delay: MOV R0,#255 DJNZ R0,$ after the read of the HCTL caused a 25% increase in roller movement has me puzzled because I POP R0 after the delay??? Jon Oh yeah...this is for work and I'm not having fun anymore. |
| Topic | Author | Date |
| 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 |



