| ??? 01/17/02 17:35 Read: times |
#18842 - RE: 8 bit address/data bus and memory I/ |
Jon,
Think i need more info. Superficially, i don't see how this delay would impact things. Is you problem consistent? Are there interrupts occuring during processing? Is there a chance that "HCTL2l" is cross defined for another variable? It looks like others are more familiar with the HCTL i've looked at the data sheet it looks like timing is not eccentric what FZ is you proc? Also an aside, do you purposely push r0 using the "push 00" to ensure r0 bank0 is pushed or doesn't you assembler accept "push ar0"? regards, p |
| Topic | Author | Date |
| 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 |