| ??? 01/17/02 17:33 Read: times |
#18841 - RE: 8 bit address/data bus and memory I/ |
The latest development. As I am waiting for other chips to arrive. I've tried the following:
1) moved the HCTL reset line to P1.0 and the 'STEP' toggle bit to P1.1 Now the only device on the address/data bus are the '573 to latch the address and the HCTL-2020. No change in results. The DJNZ delay loop added after the HCTL read still causes a longer length to be fed. Thanks so far to all that have added their input. I will be trying all suggestions until I get this resolved. Jon |
| Topic | Author | Date |
| 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/O | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
| RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 | |
RE: 8 bit address/data bus and memory I/ | 01/01/70 00:00 |