Hi gents,

Let's not get carried away now! We haven't yet figured out whether or not the *logic* of the thing is correct and I would like to clear that up first before blaming it all on the hardware.

Sascha: Is the MSb of your external counter inverted or not? That's the main issue here. For your system to work properly it should not be inverted, because the internal 8051 counter increments on the falling edge. I.e. when the signal goes from '1' to '0'. This happens when the external counter overflows from 'FF' to '00'.

So dive into your VHDL code and see to it that that is OK.

Regards,
Rob.

PS. Just a thought; your CPLD is quite large enough to implement the whole 24-bit counter! Maybe that's an idea too...