Hello Rob,
I think the same about inverting the Counter MSB output ? eh... ?
And I think my FPGA does not work right, so I used a logic gate to invert it, but it was the same problem.

Now yesterday night I found the error.
In the interrupt routine I read and copy the counter value from hardware register to temp. software register (RAM) and clear all hardware register (reset).
But my big mistake was that I first clear the counter in the controller and at least the external counter.
Is the MSB of the external counter =1 and now the reset change it to 0, the first edge is detected for the counter in the controller.
My resolution to fix the error is:
First to clear the external counter, wait for 24 clock cycle (2x NOP) and then clear the internal counter.

Now it works well, I`m so happy......

best regards to all,
Sascha