I believe that since this in an absolutely irrelevent fact as to the use of the chip, some cores may, indeed, do it on the rising and some on the falling edge of the clock. The '51 has gone through many evolutions, HMOS to CMOS, 12 clock to 6/4/1, dynamic to static and whatever other cost savings and improvemnets the designers have come up with. Specifically memory accesss timing is derivative dependent and can only be derived from the data sheet for the specific derivative.

Have fun,

Erik