I'm using logic on the RD/WR lines to generate the OE on a bus transeiver. I need to allow the TxRx time to enable itself before I issue the connected peripheral with it's clock pulse (also derived from the RD/WR)

OEs on devices connected to e.g. port0 are commonly and easily generated by using memory-mapped I/O. The address decode has plenty of time to select the route of the OE before !RD or !WR comes along.

I need to allow the TxRx time...
This commonly refer to the UART, what exactly do you mean?

Erik