I'm using logic on the RD/WR lines to generate the OE on a bus transeiver. I need to allow the TxRx time to enable itself before I issue the connected peripheral with it's clock pulse (also derived from the RD/WR)

It is my intention to use the next occuring edge of the XTAL2 signal (after assertion of RD/WR) to generate this clock signal.

So, if I know the RD/WR is always asserted on the falling edge of XTAL2, I can simply use XTAL2 (buffered) as the clock input on a spare D-type. If it always occurs on the rising edge ,however, I'll have to invert XTAL2 prior to the clock input.

Obviously, much information irrelevant to my enquiry has has been omitted.

David