| ??? 06/21/02 12:31 Read: times |
#24742 - RE: XTAL2 as external clock |
As I tried to infer, there's more to this than can be quickly explained. Suffice to say I cannot use conventional address decoding- the peripheral cannot be deslected between accesses, hence the bus tranceiver (which I referred to as TxRx).
If Peter is correct, and the relative phase between assertion of RD/WR and XTAL2 can alter during operation, then my question has been answered. David |
| Topic | Author | Date |
| XTAL2 as external clock | 01/01/70 00:00 | |
| RE: XTAL2 as external clock | 01/01/70 00:00 | |
| RE: XTAL2 as external clock more | 01/01/70 00:00 | |
| RE: XTAL2 as external clock | 01/01/70 00:00 | |
| RE: XTAL2 as external clock | 01/01/70 00:00 | |
| RE: XTAL2 as external clock | 01/01/70 00:00 | |
RE: XTAL2 as external clock | 01/01/70 00:00 |