Hi all,

How about this: 7 bytes and 7 cycles

;; INPUT: P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
;; |----|----|----|----|----|----|----|----|
;; | 0 | 0 | 0 | D3 | D2 | D1 | D0 | 0 |
;; |----|----|----|----|----|----|----|----|
;;
;; *****note: P0.7, P0.6, P0.5 and P0.0 are hardware-grounded*******
;;
;; OUTPUT: P1 = low byte, P1.7 = MSB, P1.0 = LSB
;; P2 = high byte, P2.7 = MSB, P2.0 = LSB
;;

; I'll skip the RAM init part for now.
;internal RAM should be set as the following
;P2 value on even address, P1 value on odd address
;ADD DATA
;00 00
;01 00
;02 01
;03 00
;04 02
;05 00
;
;
;0x1C 0
;0x1D 0x40
;0x1E 0
;0x1F 0x80

;; Please noted that the input from P0 is already shifted by one bit
;; decoding routine, byte(s) cycle(s)
DECODE:
mov R0, P0 ;; 2 2
mov P1, @R0 ;; 2 2
inc R0 ;;1 1
mov P2, @R0 ;; 2 2
jmp FINISH