The last '420 i obtained were @ the A-2 stepping which had a max xtal rate of 33MHZ.

Regarding no. of cycles per instruction;
Std accum referencing instructions such as ADD A,Rn, ANL A,Rn, MOV A,Rn, Mov @Ri,a and CLR C, INC DPTR execute in 1 clock cycle. Which would be 90ns for 11.0592 MHz and not using the clock doubler.

The majority of instruction (i.e. ADD A,DIRECT, MOV Rn,#data, execute in 2 clock cycles.

MUL AB and DIV AB are not equal in execution rate being 9 and 10 cyc's respectively.

It is a very cool device and the clock doubler/quadrupler allows a lot of flexibility for sio bit rates.

regards,
p