| ??? 03/12/03 14:36 Read: times |
#41339 - RE: FPGA/Erik Responding to: ???'s previous message |
I use a CPLD if that is applicable to the task at hand. However the extent I use CPLDs is to stop at 1 or 2 parts of 22V10 complexity. As a next step up I always look at FLASH based FPGA parts that have JTAG in circuit programming capability. The small parts from Lattice for example offer 64 logic cells in very small 44/48 pin packages for less than the cost of two CPLDs (considering programming, placement, and test costs) and offer in circuit re-programmability.
Michael Karas |
| Topic | Author | Date |
| FPGA | 01/01/70 00:00 | |
| RE: FPGA | 01/01/70 00:00 | |
| RE: FPGA | 01/01/70 00:00 | |
| RE: FPGA | 01/01/70 00:00 | |
| Free PDF handbook | 01/01/70 00:00 | |
| RE: Free PDF handbook | 01/01/70 00:00 | |
| RE: Free PDF handbook / Link | 01/01/70 00:00 | |
| RE: FPGA | 01/01/70 00:00 | |
| RE: FPGA | 01/01/70 00:00 | |
| RE: FPGA | 01/01/70 00:00 | |
| RE: FPGA - William | 01/01/70 00:00 | |
| RE: FPGA | 01/01/70 00:00 | |
| RE: FPGA, Mahmood Elnasser | 01/01/70 00:00 | |
| RE: FPGA, Babar | 01/01/70 00:00 | |
| RE: FPGA, Mahmood, | 01/01/70 00:00 | |
| RE: FPGA, Mahmood, | 01/01/70 00:00 | |
| RE: FPGA/Babar | 01/01/70 00:00 | |
| RE: FPGA/Mahmood | 01/01/70 00:00 | |
| RE: FPGA/Mahmood | 01/01/70 00:00 | |
| RE: FPGA/Erik | 01/01/70 00:00 | |
| RE: FPGA/Erik | 01/01/70 00:00 | |
| RE: FPGA/Erik | 01/01/70 00:00 | |
| RE: FPGA/Erik | 01/01/70 00:00 | |
RE: FPGA/Erik | 01/01/70 00:00 |