Thank you all for your responses.
I have not coded a test program yet, but I was heartened by your replies.
Josh, the purpose of this effort is to create a mechanism for an "Illegal Code Fetch" trap, similar to an illegal instruction trap. As part of establishing a CRC check for my code (which is another story), I plan to fill my unused address space with some instruction that would cause the program to vector to my trap. CLR P3.3 (or SETB) work very well if it can generate an External Interrupt 1. If the code enters in the middle of the instruction, it interprets the P3.3 address as a 1-byte CPL C instruction and then resynchronizes with the next CLR P3.3 instruction. Unfortunately, P0 and P2 will be given over the address bus, P1 is an input-only port and the other P3.x bits do not allow for a clean resynchronization. I am already using ExtInt 0, so I can't use that as my trap. (whew! that was long-winded. sorry.)

I've listened to myself talk enaough.
Thanks again for all your help.

Chris