Thank you,
you've just confirmed my thoughts that it is possible to communicate using interrupt lines and one data bus. However, I think one more line is requred. It is because there is only one bus master uC. Slave can't assert a value to the bus until master affords. Terefore, when slave has data to send, it disables interrupts line and interrupts the master. Master can have data to send at the same time. To avoid the conflict, master specifies R/W operation and asserts data value to the bus if in write operation. It informs the slave about direction via additional R/W line and starts the operation interrupting the slave. The slave has interrupts disabled waiting until the INT line becomes low. After the line does, the slave handles the R/W request, deasserts master IRQ line and proceeds. Once deasserted, the master is ACKed that data are accepted (write operation) or are valid on the bus (read operation). can proceed too. If slave still has data to send the operation is repeated.
When master has data for slave it merely does the same what has beed described for write operation. It puts value to the bus then asserts R/W to W and interrupts slave uC. uC merely calls request process operation.