Hello everybody

My requirement:
1. Two external events have to be counted. Basically RPM of two motors simultaneously.. input to processor coming in pulsed form from an opto-coupler passed through an Schmitt inverter 74hct14. RPM not more than 1K.

2. Data is to be stored in SRAM every 10 seconds. a. RPM logged every 10 seconds.
b. Some more details which are to be uploaded to the PC later on.

3. Cheapest available processor to be used so 89c51 is the choice.

4. The cost is a major major constraint and so I have to reduce the cost at any cost.
The solutions that I have already thought are not cost effective. So looking out for some more solutions..

Problems being faced:
1. If I use T0 and T1 pins on the processor (p3.4 and p3.5) I won't be able to use the internal timers for setting up delays.

2. How to save the data in the SRAM at power on and power off when the processor might go crazy and select my sram and put some junk data or corrupt the data.

Ways that I have already thought of implementing:
To solve first problem:
(i) Use an independent counter IC like 74HCT4060 and read its count after 10 seconds and do the calculations after that. (Use internal timers in this case )
(ii) Have an external timer IC may be an RTC which can give me a pulse every 10 sec so that I read the internal counters at that moment (using pins as the object or pulse counters)
Basically have separate arrangements for the timer and the pulse counter. ( one of them has to be outside the Processor).

(iii) Use higher end processors like RD2 series which 3 timers.... not thinkable .. Cost is the constraint.

To solve the second problem:
(i). Already the power to the SRAM is given from a 4.5V battery source. Arrangement of 3 AA size cells in series. Wish to separate the power of all the devices like the buffers and the address decoders so that nothing should be able to trigger the pin CS of the SRAM till the time processor is not stable. Planning to use a relay controlled by the processor.

(ii). Use a processor-controlled shutdown of the power-supply i.e. the voltage regulator. with micro-controller supervisor IC.

(iii) Use some kind of RC delay so that the processor control and the CS pin of SRAM are separated somehow for sometime till the time processor stabilizes ( at the time of power on ) and again trigger so that they are isolated when processor is shutting down.
actually I am using 74ls138 for address decoding .. was also wondering if I can do anything with the select enables of it. It has got 3 pins as enables.


I hope I have given adequate information for all to understand and respond to my query.
Please come up with some cheap solution to my problem soon ...
Any other suggestions are also welcome.
Thanks in advance
nitin