well i was just discussing my SRAM problem with someone who told me that the only thing i need to solve my problems is separating the power of SRAM and rest of the board and that RESET capacitor should be a large value as according to him :

1. At power Off no problems will be encountered as the processor will be doing some pre-defined functions ( unless it was writing something to the SRAM at power OFF , the only data that can be corrupted) and the processor would not have enabled the CS.

2. At power ON i.e. at RESET or during RESET all the pins will either be floating or having a fixed value ( according to him a pre-requisite of processor design ) and so design the board accordingly that the SRAM is not selected at POWER ON. he also asked me to use a larger valued capacitor so that the processor gets enough time to "WAKE UP AND DO DAILY CHORES" :-)


would anyone here through some light in this regard and also direct me to some thread or site where i can find details as to what happens to the processor at the time of RESET and also what values are present at pins of 8051, as i remembered reading that at bootup/power on 8051 pin states aren't guaranteed only after reset all ports will have FFh data on them.

i did try searching in the thread and gave search topic as " at reset " and i got more than 2000 matches so please help me out. also didn't find any details in this regard at FAQ. i am sorry in advance if i missed but someone please be kind enough and show me the way ...
regards
nitin