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11/12/03 10:00
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#58368 - Memory interfacing problem
Hello
I am interfacing AT89C52 with DP RAM IDT7130.
I wrote a simple program for writing on to five location.
DP ram has the flowwing control lines
CE_(active low), R/W_(WRITE active low,READ active high),
BUSY_(active low),INT_(active low),OE_(active low)
and the rest are address and data lines on both side.
i have connected AT89C52 on only right side of DP RAM , while the other side is left floating.
The control lines are as connected:
CE_ ---- i toggle it using p3.2
R/W_ ---- connected to WR_ of 8051
busy_ --- floating
INT_ ---- floating
OE_ ---- conected to RD_ of 8051

however when i write to RAM using movx @dptr,a
i dont get a low signal on WR_ of 8051 ,so no question of writing to DP RAM. I have checked the WR_ signal on storage oscilloscope at 250 nsec.

what may be the problem.

Thanks,
Pravin

List of 20 messages in thread
TopicAuthorDate
Memory interfacing problem            01/01/70 00:00      
   RE: Memory interfacing problem            01/01/70 00:00      
      RE: Memory interfacing problem            01/01/70 00:00      
         RE: Memory interfacing problem            01/01/70 00:00      
            RE: bull            01/01/70 00:00      
   !WR output destroyed?            01/01/70 00:00      
      RE: !WR output destroyed?            01/01/70 00:00      
         RE: !WR output destroyed?            01/01/70 00:00      
            RE: !WR output destroyed?            01/01/70 00:00      
               RE: !WR output destroyed?            01/01/70 00:00      
   RE: Memory interfacing problem            01/01/70 00:00      
      RE: Memory interfacing problem            01/01/70 00:00      
         RE: Memory interfacing problem            01/01/70 00:00      
            RE: Memory interfacing problem            01/01/70 00:00      
   RE: Memory interfacing problem            01/01/70 00:00      
      RE: Memory interfacing problem            01/01/70 00:00      
         RE: Memory interfacing problem            01/01/70 00:00      
            RE: Memory interfacing problem            01/01/70 00:00      
   RE: Memory interfacing problem            01/01/70 00:00      
      RE: Memory interfacing problem            01/01/70 00:00      

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