Read the data sheet CAREFULLY! Dual port ram isn't quite the magic thing we expect - there is some dependencies on both sides: ie don't write to the same location the other side is reading/writing. It is probably not a good idea to have the other side floating - tie it's control lines.

As an aside, many years a senior engineer designed a unit that would combine many sources of multiplexed lighting control into one multiplexed output with the highest level of each channel winning. There was an input module for each multiplexed source that put the levels into a dual port ram. A cpu would then read each channel from the other side of the dual port rams and pick the highest value then output it, and then do the next channel.........
This happened asynchronously to the inputs. Every so often there would be a disco effect on the output that had the senior engineer stumped. Me being the spotty junior tried to explain about the realities of dual port ram being that if a new value was being written whilst we're reading the same location on the other side we will get garbage - the senior engineer argued that you would either get the old value or the new value - nope! you'll get ANYTHING. The solution was to synchronise the reading on one half of a clock and the writing on the other half of the clock thus guaranteeing no collision could occur. This feature is normally not spelt out in the datasheet but hidden as some obscure spec. As with all clocked logic, SETUP and HOLD times must be obeyed. But I digress.......