I think the best way would be to use something like the cd4097 pll and use that to ensure that the processor clock is in phase with the slower clock.I have done a more complex scheme recently for locking a 25Mhz and eventualy a 100Mhz clock to a 10 Khz signal but that used the delay locked loops inside a xilinx spartan FPGA so its perhaps overkill....unless of course you stick my 8052 core in a xilinx FPGA and use my sync-o-tron to drive the processor clock.