| ??? 11/27/03 17:04 Read: times |
#59551 - RE: Syncing to a fast clock Responding to: ???'s previous message |
Now we might be getting somewhere!
In Section 5.3.6 (pg. 23) it shows the Bit Clock Frequency as 32*FSYNC (typical), but MCLK/2 (maximum). Since FSYNC=MCLK/256, this says that BCLK can be as high as MCLK/2 or 1.024 MHz in my case. Of course, this is what you suggested: The way I see it so far, you can use Fclk to interrupt the cpu, which then reads the part as fast as it can, then waits for the next Fclk edge. Drew Rainwater |
| Topic | Author | Date |
| Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock--Explained | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 | |
| RE: Syncing to a fast clock | 01/01/70 00:00 |