Erik,

Maybe I am misunderstanding you. Are you saying that the IE0 interrupt will not interrupt the RI or TI interrupt, in the middle of servicing the RI or TI interrupt? What happens if you are using IE0, IE1, TF0, TF1 and they all interrupt the serial interrupt routine(admittedly a worst case scenario)? Assume each interrupt routine is 100 usec long. That adds up to 400 usec and now you miss a character @ 28.8 kbaud. This is the one criticism I have of the 8052, that the RI/TI interrupt should have been the highest priority.
I guess I can agree to disagree on this point.
Your rules will keep you out of trouble 99.9% of the time.

Jacob