oops,
thanks for this point. Atmel has updated their datasheets and as always they made yet new "surpises". Previous datasheet I had, has neither said about that point nor shown such figure. Seems I need to look at another vendor than Atmel. Many times they create a device then after some months/years its errata appears, they change datasheets etc. Even now: they drawn nice Figure 43 you talk about, and what? No timings are indicated. How long PSEN should not be tied to GND, how long may PSEN be grounded after reset goes out, etc.
So such things make Atmel`s chips unusable: any time I have got PCB ready-to-use, they make new erratas or changes which compel me to do additional framework. Thanks God I use Altera PLD and it helps me to fix issue you indicated.

Regards,
Oleg