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???
02/18/04 09:18
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#65000 - RE: ISP cable AT89C51RD2
Responding to: ???'s previous message
Okay, I can imagine what does it mean:
To ensure correct microcontroller startup, the PSEN pin should not be tied to ground during power-on

But I cannot understand: what is the duration of "power-on"? Is it the time while Vcc stabilizes [+OSC +some internal hardware setups]. Look at this picture:



After power is switched on then there is some time while it comes to valid conditions. At this time an external Power SV chip generates reset signal. MCU power ups internaly after its internal power monitor detects correct value of Vcc, stabilized OSC and +1024 its clocks. As I understand from Atmel note, I should not connect PSEN to ground for this time. But here is the problem: this time cannot be calculated due it depends on conditions I indicated above. So I have two limits:
- I must wait till MCU power-ups internally and I do not know this time;
- I must put PSEN low before my external power SV takes off its Reset signal.
Okay, I use Altera PLD and so it is not a problem for me to solve this problem: I just keep Reset signal, let say for a second, after my SV chip deactivated it. Then I put PSEN low and keep off Reset signal.

Another thing is time when I should realize PSEN signal. Atmel says:
As PSEN is a an output port in normal operating mode after reset, user application should take care to release PSEN after falling edge of reset signal. The hardware conditions are sampled at reset signal falling edge, thus they can be released at any time when reset input is low.

Due this note, PSEN may be realized any time after reset goes low (no hold time is specified!). So by other words PSEN may be tied to ground ALL the time, isn`t it??? But it is nonsense at least because two points:
- PSEN is not open drain pin. It is two-states one (am I wrong?). And it should produce strong "1" to drive /CE or /RD of external program memory. Will the PSEN pin not be overloaded if connected to ground permanently?
- there are devices which have not 64kb of internal flash and so they may execute/read the program code from external memory even in boot-mode (user may create own bootloader which reads external memory connected as program one). In this case PSEN signal must be realized BEFORE the first command is fetched/executed.

Atmel have not indicated these conditions and so it looks like they have some crystal elaboration problems. And Atmel tries to fix them with these "notes". Not good and not honestly.

Regards,
Oleg

List of 40 messages in thread
TopicAuthorDate
ISP cable AT89C51RD2            01/01/70 00:00      
   RE: ISP cable AT89C51RD2            01/01/70 00:00      
   RE: ISP cable AT89C51RD2            01/01/70 00:00      
      RE: ISP cable AT89C51RD2            01/01/70 00:00      
         RE: ISP, SPI and me            01/01/70 00:00      
      RE: ISP cable AT89C51RD2            01/01/70 00:00      
         RE: ISP cable AT89C51RD2            01/01/70 00:00      
            Mixed Meanings?            01/01/70 00:00      
               RE: Mixed Meanings?            01/01/70 00:00      
                  RE: Mixed Meanings?            01/01/70 00:00      
                     RE: Sorry:            01/01/70 00:00      
                        RE: Sorry:            01/01/70 00:00      
                  RE: TLAs            01/01/70 00:00      
                     RE: TLAs            01/01/70 00:00      
                        RE: TLAs            01/01/70 00:00      
                           RE: TLAs            01/01/70 00:00      
   RE: ISP cable AT89C51RD2            01/01/70 00:00      
   RE: ISP cable AT89C51RD2            01/01/70 00:00      
      RE: ISP cable AT89C51RD2            01/01/70 00:00      
         RE: ISP cable AT89C51RD2            01/01/70 00:00      
            RE: ISP cable AT89C51RD2            01/01/70 00:00      
               RE: ISP cable AT89C51RD2            01/01/70 00:00      
                  RE: ISP cable AT89C51RD2            01/01/70 00:00      
               RE: ISP cable AT89C51RD2            01/01/70 00:00      
                  RE: ISP cable AT89C51RD2            01/01/70 00:00      
      RE: ISP cable AT89C51RD2; PS            01/01/70 00:00      
   RE: ISP cable AT89C51RD2            01/01/70 00:00      
      RE: ISP cable AT89C51RD2            01/01/70 00:00      
         RE: ISP cable AT89C51RD2            01/01/70 00:00      
            RE: ISP cable AT89C51RD2            01/01/70 00:00      
         RE: ISP cable AT89C51RD2            01/01/70 00:00      
            RE: ISP cable AT89C51RD2            01/01/70 00:00      
               RE: ISP cable AT89C51RD2            01/01/70 00:00      
                  RE: ISP cable AT89C51RD2            01/01/70 00:00      
                     RE: ISP cable AT89C51RD2            01/01/70 00:00      
                        RE: ISP cable AT89C51RD2            01/01/70 00:00      
                           RE: ISP cable AT89C51RD2            01/01/70 00:00      
                              RE: ISP cable AT89C51RD2            01/01/70 00:00      
                              RE: ISP cable AT89C51RD2            01/01/70 00:00      
                              HELP ME TO PROGRAM AT89C51RD2            01/01/70 00:00      

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