hi,

i am doing this application that requires an "edge triggered" exeternal interrupt. i don't have problems with codings as well as interrupt principles.

what i am bothered about is that the "edge" actually comes from an op-amp comparator output that varies from 0v - 5v. an op-amp (being analog in nature) still suffers the "unnoticeable" lag before swinging its output voltage.

now, what i am after is the duration of how long should an "edge" be before transition such that the 8051 can recognize it as a valid "edge"?

i tried to look for this info in the "bible" found on the left menu (philips), but the ac characeristics that i found only pertain to the external program/data cycles.

** as much as possible i would like to eliminate the use of 74hc14 (hex schmitt trigger) since i would only use 1 gate for that ic... (5 gates would be wasted, as well as quite a number of square mils of board space would be taken).

thanks...