hi,

Andy, you said: All the 8051 needs is a good, clean edge

Why? AFAIK, external interrupt input pin of 8051 is not used as a clock pulse. It is just examined and latched with internal clock. Hardware manual, I have says:

In edge-triggered mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, interrupt request flag IEx in TCON is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. If the external interrupt is transition-activated, the external source has to hold the request pin high for
at least one cycle, and then hold it low for at least one cycle to ensure that the transition is seen so that interrupt request flag IEx will be set. IEx will be automatically cleared by the CPU when the service routine is called.

So it does not require for sharp edges; nevertheless it must be debounced to avoid false twice-detection.
From other side, the rise/fall edges` time may be calculaed (approximately).
For example, I take datasheet of T89C51CC01.
Its input low voltage V_IL is 0.9V (max), input high voltage V_IH is 1.9V (min). So it means that difference (not recognized state level) is 1.9-0.9=1V. Now let say that OSC frequency is 12MHz and so "12 oscillator periods to ensure sampling" take 1us. It means that interrupt source must produce signal edges with speed not less than 1V per 1us. Otherwise there is a chance that MCU detects false/undefined level twice and it may produce false second interrupt (in fact it is not so bad due ISR latency). If interrupt source produces linear edge within 0...5V so it must do full switch not less than in 5us. It is maximal time; I think that 1us may be safe value for edge time. But of course it is only for indicated conditions: T89C51CC01, 12MHz, X1 mode, linear edge form. For other derivatives it may be calculated yourself.

Regards,
Oleg