Yes, it is true for the HD44780 chip. In such cases if the rise time or fall time is slower than specified, then maybe the relevant pulse will be missed at the concerned input. Question is, what is the reason for such a specification ? What kind of input structure will impose such a condition?

Strange, isn't it? I have no idea. From slow flip-flops I know about metastable characteristics. And from delay lines using propagation delay of logic gates, I know, that slow edges can cause undefined states. But in any case this specification has to do with a design mistake of internal hardware, I believe.

Kai