Hallo Michael,

to 1):

1) Many times the strobe signal goes on board and must operate a number of separate internal circuits in parallel (i.e. the signal goes to multiple internal gates and flipflops). If the input signal has slow rise time it will cause the internal circuits to trigger at different times depending on the logic threshold voltages of the various circuits. Some times this can make logic that is supposed to operate "synchronous" to operate in an asynchronous manner. This can lead to flipflop state machines going to the wrong or invalid states.

This mechanism I had in mind, when stating about the delay line. One remedy to overcome such problems is to use a common buffer directly at the input, which then delivers a synchronous signal to all paralleled stages. And the absence of such a common buffer is what I call design mistake...

By the way, this a typical mistake when beginners design digital circuits. The omitting of such a common buffer at input is often the cause of a heavy violation of timing specifications and finally results in total desaster.

to 3):

3) To equip the input receiver circuits on an IC with Schmidt trigger inputs has a tendancy to slow down the propagation delay of the input circuit. Such capability would make inputs much more tolerant to slow rise times but at the expense of performance. So this leads to a design tradeoff on the part of the chip designer to eliminate the input hysterisis im favor of attaining the faster circuit operation.

Yes, but a rise and fall time specification of less than 25nsec is a bit strange, if you keep in mind that even 74HCMOS accepts rise and fall times of up to 500nsec, isn't it?

May be I'm wrong, but a good design should not have such a heavy restriction on transistion time.


Regards,
Kai