Hi Bartosz,

In Oleg's example, disabling interrupts is neccesary because the watchdog timer reset depends on a register being written to in two consecutive cycles. So, if an interrupt occurs directly after the first write, the WDT will not be reset.
Call it "manufacturer's fancy" if you will, but it is actually sound design, because the chance of runaway code producing the exact sequence required is very, very small indeed.


Regards,
Rob.