??? 08/19/04 02:53 Read: times |
#76139 - RE: debouncing code using vertical counters Responding to: ???'s previous message |
I did a project back in the about 1983 timeframe wherein an 8-bit microcontroller (a HD6303Y I believe) had to perform a task of filtering and state decoding 32 separate telephone lines for ringing/on hook/off hook/hook flash states. Each line was interfaced with a comparator that detected whether the voltage across the phone line was above or below some nominal 13->17 volt level. All 32 comparator outputs were wired to a hardware circuit that combined the bits into a serial bit stream of four bytes at 19.2K baud with start bits, a "parity" bit and a stop bit just like one would see on a UART wire. The four bytes were sent continuously in a frame that repeated endlessly. The "parity" bit was set on the first byte of the 4 byte frame and cleared on the other three bytes and performed the function of a marker for frame sync.
The microcontroller received this serial data stream via its UART and processed all the bits via stacks of 4 byte sets that were organized as vertical counters, vertical shift register filters, state variables and so forth. A state machine was able to then decode the status of any line as ON_HOOK, OFF_HOOK, RINGING_PULSE, RINGING_PULSE_COUNTER, and HOOK_FLASH_TIMER for all 32 telephone lines. Using this scheme I was able to deduce the proper states for all the lines using about 5% of the processor bandwidth!! It was a job that other programmers at the time thought would require a separate microcontroller for each 8 lines if it was possible at all!! I found vertical logic very easy to implement. It was done by doing a paper design for a complete single phone line filter using logic gates and flip-flops. A filter became then a shift register of some flop-flops in series and a counter became implemented as a bit serial adder/incrementer using gating and flip-flops. After I perfected the paper design the flip-flops became bits in memory locations and the logic gates became AND, XOR, and NOT instructions of the micro controller. Parallelism was handled by extending the logic across sets of 4 bytes to 32 bits wide. The clocking of the flip-flops became the state machine timing. Rather than use a timer interrupt for the state clocking I used the regular rate of the UART interrupt as the state machine trigger. As I said above the UART was receiving continuously at a regular rate. The logic routines were written to handle a byte wide swath through the 32-bit wide "data registers" by using an indexed addressing mode with the index set to 0, 1, 2, or 3. At the time I even amazed myself at how well it ended up working. Michael Karas |
Topic | Author | Date |
debouncing code using vertical counters | 01/01/70 00:00 | |
RE: debouncing code using vertical count | 01/01/70 00:00 | |
RE: debouncing code using vertical count | 01/01/70 00:00 | |
RE: debouncing code using vertical counters | 01/01/70 00:00 | |
RE: debouncing code using vertical count | 01/01/70 00:00 | |
RE: debouncing code using vertical counters | 01/01/70 00:00 | |
RE: debouncing code using vertical count | 01/01/70 00:00 | |
RE: debouncing code using vertical count | 01/01/70 00:00 | |
RE: debouncing code using vertical counters | 01/01/70 00:00 | |
RE: debouncing code using vertical count | 01/01/70 00:00 | |
RE: debouncing code using vertical counters | 01/01/70 00:00 | |
RE: debouncing code using vertical counters![]() | 01/01/70 00:00 |