I was trying to implement the 32 lines sampling technique at first using conventional logic of doing one at a time. It was very clear almost immediately that the solution would not have enough bandwidth even on 4 or 5 processors and thus the source of doubt on the part of the companies in-house programmers. I had been hired as a consultant to come in and work out a solution. The sheer number of logic operations pointed to the need for parallelism and so, as I recall, I decided to "do eight at a time" via the processors byte arithmetic. I did not have any other reference code to look at to observe a prior similar solution but I was aware of the concept of the bit-wise parallel processing. The scheme of doing the logic design before hand on paper was just something I came up with on my own. As a matter of fact I almost was going to make an actual realization of the circuit in hardware on one of those plugboard test panels but came to the realization that the state machine code in software could be modularized with macros anyway and so the code implementation became a very straight forward and easy to change as I debugged it. I did not even have to really worry about making the a minimal code path length through the logic becasue it turned out to require so little actual bandwidth. The HD6303Y processor from Hitachi at the time had an A/B register accumulator type instruction set much like the Mot 6803 processor family and so writing assembler to implement the logic was rather easy.

I have since that time built countless implementations of filters and debouncers using shift register type implementations that are 8 or 16 bits wide. Even use the technique on several PC based industrial controllers where the software is coded in C.

Michael Karas