It still can damage a chip, but the chance is far lower if all the charge stored in you would cross it.

Yes, that's true. But even only charging up the 'free' chip, which is assumed to be hanging 'in air' can be very dangerous (for the chip). There's a reason, why antistatic bags, humidifiers, ionizers and wrist straps must be used, when handling unsoldered chips...

Let's have a brief discussion about the ESD stress, that is imposed, when touching a chip which isn't connected to anything:

Assume, you walk across a carpet at 10-20% relative humidity. Then your body becomes charged to up to 35kV. 'Human body model', which models this situation assumes now, that your body and the grounded surrounding form a capacitance of about 100pF, while your body is the one electrode and ground (earth, soil) is the other. This 100pF widely differs of course from case to case. So, take it as approximation of order of magnitude.

Now consider the free chip: From what we know about a simple piece of wire, we can estimate its capacitance to surrounding: A piece of wire of 1cm length shows an intrinsic space charge capacitance of about 1.8pF. So, a chip can be assumed to have a capacitance of about 2pF to the surrounding. Again, this is only a rough approximation about order of magnitude.

If you now touch the chip at a pin, then this is very similar to the situation, where a charged capacitor is connected to a second, uncharged one. In our case 100pF, charged up to 35kV is partially discharged by connecting the uncharged chip capacitance in pararallel. As the total unchanged charge must share the bigger capacitance of 100pF + 2pF, the parallel combination will show a voltage of 35kV x 100pF / 102pF = 34.3kV. So, the resulting voltage is only a bit smaller than 35kV.

In order to calculate the stress of this discharge, we want to think about the heating of die structures caused by the discharge current:
Human body model assumes, that body impedance limits ESD current, as if body shows an impedance of 1500 Ohm. Again, this is only a rough approximation. But it helps us to estimate the height of discharge current into the chip: At the instant, when the chip is touched, all the voltage of body capacitance drops across 1500 Ohm resistance, yielding a peak current of 35kV / 1500Ohm = 23.3A. Well, that's a rather big current, isn't it? By the way, 'machine model' assumes a much lower discharge impedance than 'human body model'...

The discharge current into the chip decreases following an exponential curve with a time constant 'tau' of Rb =1500Ohm (R of body) times the series capacitance of Cbody =100pF (C of body) and Cc = 2pF (C of chip) , which is tau = 1500Ohm x 1.96pF = 2.9nsec.

Assume now, that the discharge current flows internally of chip through some piece of conductor. Think for instance of connections made of evaporated aluminium, which connect the individual pn junctions or processed substrate elements to each other. The ohmic resistance of such an evaporated aluminum conductor is called Ra.

The heating of Ra caused by discharge current is dW = I(t) ^2 x Ra x dt. It can be shown, that the integral over this term is W = I(0)^2 x Ra x tau / 2 which is W = (Ue / Rb)^2 x Ra x tau / 2, where Ue = 35kV, the original body voltage.

To what temperature will Ra rise, due to the heat energy W, means what about dT?

dT = W / m / c

m is the mass of Ra, means the mass of evaporated aluminium conductor, c is the specific heat of aluminium, which is c = 900J / kg / K.

m can be calculated by the help of density of aluminium 'da' and from the volume of evaporated aluminium conductor, which shows a cross section 'A' and a length 'l'. We get m = da x A x l.

And when we assume Ra = ra x l / A, where ra = 0.028 x 10^-6 Ohm x m is the specific resistance of aluminium, then this leads to:

dT = W / m / c = ((Ue / Rb)^2 x ra x l / A x tau / 2) / (da x A x l x c) =

((Ue / Rb)^2 x ra x tau) / (2 x da x c x A^2)

It's interesting to note, that this formula only contains the cross section 'A' of evaporated aluminium conductor, but not its length 'l'!

It's obvious, that the heating dT is maximal at those points, where 'A' is minimal, means where the evaporated aluminium conductor shows a 'bottleneck'. These points showing a low 'A', are prone to become damaged first, when an ESD event hits the chip!

Now, let's have some examples:

With da = 2.7 x 10^3 kg / m^3 and A = 100nm x 100µm it follows dT = 91K.

This is acceptable, but what if structures are much smaller, what can be seen with high integrated chips? What if A = 100nm x 10µm? Then dT = 9096K !!

Ok, it's unprobable, that the whole current is flowing through such a bottleneck. But who knows where the current actually flows on die, when you touch the pin of a free chip??

It's a matter of fact, that free chips indeed become damaged, when being touched by charged persons, means, if an ESD event occurs. And from above formula it can be seen, that the stress on die structures increase with 1 / A^2, means that progress of integration of chips drastically increases the susceptibility against damage due to ESD events, unless manufacturers implement certain protection measures being suited to divert ESD currents on die as much as possible.


Kai