Please be patient with me as this is my first post to this site.

I’m having trouble with interrupts on an Phillips 80C32. The micro has 256 bytes of internal RAM, 64k of external RAM, and 64K of external PROM. The crystal is 24Mhz.

The application requires two interrupts; one at 10ms that performs the real time tasks for the application. The second is at 5ms that performs some time critical data acquisition. The 10ms ISR requires about 7ms to execute. The 5ms ISR runs in about 1ms. The design specifies that the 5ms ISR should have priority over the 10ms ISR.

The 10ms ISR is initiated by external interrupt 0 (EX0). The source of this interrupt is from a separate circuit. One of the first tasks of the 10ms ISR is to program internal timer 0 to overflow in 5ms seconds. Timer 0 uses the internal clock. Timer 0 overflow interrupt (ET0) is used to initiate the 5ms ISR.

As currently implemented, the 10ms interrupt is recognized and completes before the 5ms ISR is performed. This is incorrect. The 10ms ISR should be interrupted when timer0 overflows resulting in the 5ms ISR being performed. When the 5ms ISR completes program control is passed back to the 10ms ISR. When the 10ms ISR completes, program control is passed to lower priority, non-time critical tasks. The whole sequence repeats every 10ms.

Code setting PT0 of the interrupt priority register is executed during the power up of the system but reads of the IP register during the 10ms ISR do not report that the priority has been recognized. The failure of the high priority for PT0 to be recognized is the most likely explanation for the incorrect sequencing of the ISRs

Are there any tricks to programming the priority? For example, does the interrupt need to be enabled or disabled when the priority is programmed. Is the priority retained after the ISR completes? Are there any timing issues with programming the interrupt?