I inherited this program about 8 years ago. We have a product line that is based of derivatives of this code. When I took over all the O/S stuff was done. I mainly have been involved in the applications.

The monitor is supported in my 10ms ISR. Its not very sophisticated. We just call the 485 exec once per 10ms and respond to commands. This monitor is for test only. The UART stuff is handled in a ASIC that buffers the incoming commands and takes care of outgoing responses. I just look in one memory location for input and write the output to another. Long story short...the only interrupt needed to support the monitor is the 10ms one.

The code was designed without use of the priorities. During the early days of the product the 10ms ISR took less than 5ms to complete so it had executed its RETI before the 5ms (timer0) interrupt occurred. Since then it has grown to require more than 5ms and that is when the problems started. We didn't notice this until recently since the code provides no visible symptoms that the 5ms interrupt is late. It fails to report a low probabability error with this problem. The controller that this code goes into has a second micro (8086) which redundantly computes that same error so when we tested the fault the other processor reported it and we overlooked that the 8032 was not reporting it.

I commented out enough of the 10ms ISR tasks to get it back below 5ms and then it works.

Is there any pit falls in dynamically controlling the interrupts? Currently, the 10ms ISR is enabled at all times. It programs timer0 and enables the 5ms interrupt (ET0) at the beginning of each 10ms frame. The 5ms ISR disables the interrupt when it completes. I'd prefer to just program them once and let them run.

In previous attempts to read back the IP I put the diagnostic code in the 10ms ISR. I like the idea of spreading them around. I'll give that a try tomorrow. I particularly like the idea of a read back right after programming the SFR just to see if the data every gets recognized.

I'm also very interested to try out option 3 since the registers are declared in one of our ASM modules. I'll attach some of that below.

This is how the code knows where the SFRs are:

int_enable data 0A8H ;Microcontroller Register
int_priority data 0B8H ;Interrupt Priority Register
stack_pointer data 081H ;Microcontroller Stack Pointer Register
rs485_cntl data 098H ;Serial Port Control Register
rs485_data data 099H ;Serial Port Data Register.
timer0_lo data 08AH ;Timer/Counter 1 Low Byte
timer0_hi data 08CH ;Timer/Counter 1 high Byte
timer1_lo data 08BH ;Timer/Counter 1 Low Byte
timer1_hi data 08DH ;Timer/Counter 1 high Byte
timer2_con data 0C8H ;Timer/Counter 2 control
timer2_lo data 0CCH ;Timer/Counter 1 Low Byte
timer2_hi data 0CDH ;Timer/Counter 1 high Byte
timer_con data 088H ;Timer/Counter control
timer_mod data 089H ;Timer/Counter mode control
mc_psw data 0D0H ;Program status word
mc_acc data 0E0H ;Microcontroller's Accumulator.
mc_port1 data 090H ;Microcontroller's port 1.
mc_pcon data 087H ;Microcontroller's PCON register
mc_dpl data 082H ;Microcontroller's DPL register;
mc_dph data 083H ;Microcontroller's DPH register;
mc_b data 0F0H ;Microcontroller's B register

The bits of the SFR are broken out as follows:

;*****************************************************************************
;Bit Definition for Interrupt Enable register
;*****************************************************************************

rtc_int bit int_enable.0 ;Bit 0 External Interrupt 0
sub_rtc_int bit int_enable.1 ;Bit 1 Timer 0 Interrupt
master_int_en bit int_enable.7 ;Bit 7 Master Interrupt Enable

;*****************************************************************************
;Bit Definition for Interrupt Priority register
;*****************************************************************************

rtc_int_priority bit int_priority.0 ;Bit 0 External Interrupt 0 priority
sub_rtc_int_priority bit int_priority.1 ;Bit 1 Timer 0 Interrupt priority


sorry about the wraparound. Thanks for you interest. I'll let you know how things progress. have a good weekend.