Well I know nothing about html but I managed to produce this listing using gvim to colour the syntax,expand the tabs and convert to html,all without my hands leaving my arms at any time.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity vga is
 port(

            clk         : in    std_logic;      ---25.175 Mhz clk
            reset       : in    std_logic;
            addr_data   : in   unsigned (7 downto 0);
            addr_high   : in   unsigned (7 downto 0);
            write       : in    std_logic;
            ale         : in    std_logic;
            psen_n      : in    std_logic;
            rd_n        : in    std_logic;
            wr_n        : in    std_logic;
            hsync       : out   std_logic;
            vsync       : out   std_logic;
            red         : out   std_logic;
            green       : out   std_logic;
            blue        : out   std_logic;
            int_n       : out   std_logic
           );

end vga;


architecture rtl of vga is
type UC_STATE_TYPE is (IDLE, ADDR_DECODE,ADDR_MATCH, DATA_TRS, END_CYCLE);
signal prs_state, next_state : UC_STATE_TYPE;
signal colour,row,column,reg_addr : unsigned (7 downto 0);
signal ale_i,psen_i,wr_i,rd_i,done_screen_i,write_i :std_logic;
constant upper_addr :unsigned:=X"FF";   ---register addresses
constant colour_reg :unsigned:=X"00";
constant row_reg    :unsigned:=X"01";
constant col_reg    :unsigned:=X"02";
component  vgacon
port( clock   : in  std_logic;
     resetn   : in  std_logic;
     row      : in  std_logic_vector(5 downto 0);
      col     : in  std_logic_vector( 5 downto 0 );
     colour   : in  std_logic_vector(2 downto 0);
     do_write : in  std_logic;
     hsync    :out std_logic;
     vsync    : out std_logic;
     data_r      : out std_logic;
    data_g       : out std_logic;
    data_b       : out std_logic;
    done_screen  : out std_logic );
end component;


begin

vgacon1:vgacon port map( clock=>clk,
                resetn=>reset,
                row=>std_logic_vector(row(5 downto 0)),
                col=> std_logic_vector(column(5 downto 0 )),
                colour=>std_logic_vector(colour(2 downto 0)),
                do_write=>write_i,
                hsync=>hsync,
                vsync=>vsync,
                data_r=>red,
                data_g=>green,
                data_b=>blue,
                done_screen=>done_screen_i);

int_n<= not(done_screen_i);     ---make this open drain to allow wired_or

sync:process(clk)
begin
        if rising_edge(clk) then
                ale_i<=ale;
                psen_i<=psen_n;
                rd_i<=rd_n;
                wr_i<=wr_n;
                write_i<=write;
        end if;
end process;



UC_REGS: process (clk)
begin

        if rising_edge(clk) then
                if reset = '0' then
                    prs_state <= IDLE;
                else
                    prs_state <= next_state;
                end if;

        end if;

end process;


Uc_decode: process (prs_state,addr_high,addr_data)

begin

        case prs_state is
        when IDLE =>

                if ale_i='1' and psen_i = '1' then
                next_state <= ADDR_DECODE;
                end if;

        when ADDR_DECODE =>
                if ale_i='0' then
                        if (addr_high=upper_addr and (addr_data=colour_reg or addr_data=col_reg or addr_data=row_reg)) then
                        reg_addr<=addr_data;
                        next_state<=addr_match;
                        else next_state <=idle;
                        end if;
                end if;

        when ADDR_MATCH =>

                if wr_i='0' then
                        case reg_addr is
                        when colour_reg=>colour<=addr_data;
                        when col_reg=>column<=addr_data;
                        when row_reg=>row<=addr_data;
                        when others =>null;
                        end case;
                end if;
                next_state<=data_trs;

        when DATA_TRS =>

        if rd_i = '1' and wr_i = '1' then
                next_state <= END_CYCLE;
        end if;

        when END_CYCLE =>

        if ale_i = '0' then
        next_state <= IDLE;
        end if;


        end case;

end process;

    end rtl;