| ??? 11/20/07 20:56 Modified: 11/20/07 22:45 Read: times |
#147277 - Tri-state busses in FPGAs |
Inside an FPGA, you could make a 2-to-1 multiplexer with a couple of tri-state buffers driving a common line, or with a little AND-OR network. This picture shows both ways:
 What are the considerations that would recommend one of these over the other? On the surface, the first method (with the tri-state buffers) seems like it would involve less hardware and might be a little faster. But I saw something the other day that said it's best to avoid tri-state busses inside an FPGA. Can anybody say if that's a generally true statement, and if so, why? Thanks, -- Russ |
| Topic | Author | Date |
| Tri-state busses in FPGAs | 01/01/70 00:00 | |
| Tristate Buffers (TBUFs) have been phased out | 01/01/70 00:00 | |
| Thank you | 01/01/70 00:00 | |
| Closing the loop | 01/01/70 00:00 | |
| siumulate? | 01/01/70 00:00 | |
| I didn't simulate it (yet) | 01/01/70 00:00 | |
| hmmm | 01/01/70 00:00 | |
| So ... what about a BIG multi-party bus? | 01/01/70 00:00 | |
| delay | 01/01/70 00:00 | |
| nevertheless ... | 01/01/70 00:00 | |
| re: nevertheless | 01/01/70 00:00 | |
| What disappoints me is the advertising vs reality | 01/01/70 00:00 | |
| advertising | 01/01/70 00:00 | |
| advertising, badvertising ... lies! | 01/01/70 00:00 | |
| oy | 01/01/70 00:00 | |
If only one could rely on them ... | 01/01/70 00:00 | |
| largely, it's because it's not an option | 01/01/70 00:00 | |
| Zackly | 01/01/70 00:00 | |
| If you have internal tristate resources ... | 01/01/70 00:00 | |
| I have new worries now | 01/01/70 00:00 | |
| tristates in FPGAs | 01/01/70 00:00 |