Interesting. I tried a few different ways to make some multi-sourced tristate signals inside the FPGA, and the synthesizer quite consistently replaced them with logic every time. "Well!" I said, "Let's see what it does with this!"

module abuse (
    input a,
    input b, 
    input selectA,
    input selectB,
    output w
    );

    assign w = selectA ? a : 1'bz;
    assign w = selectB ? b : 1'bz;

endmodule

I thought it might freak out at the possibility of selectA and selectB both being asserted at the same time. But no, in that case it just put a | b onto the output. I suppose somebody with a little more ambition than I have could find the rules that govern a case like that. For now, anyway, I'm content with a simple "don't do that!"

-- Russ