Hi again.!
San, thanks for advice, but i've consume my quotes of samples,
next time I need 10k..!!

Sanjeev, I think that I already abandon the idea of using SPI-bus-
communication between the two uP's, becouse the slave-uP's
is a master when it handles the 4K-E2 SPI-memory.
So I can agree with Peter D, If I have a clean comm between
the CPU's it's certainly no probs, bu I have hang a lots of
SPI-components around both the 'master-uP's and the 'slave-uP's.
So, to avoid a lots of problems, I will solve the cpu-communication
in another way.

Regards Magnus Munthe