| ??? 03/15/01 08:27 Read: times |
#9998 - RE: Multipple processord with SPI? |
Hi Sanjeev,
it seems, you know not the AT89S8252, the only 8051 derivate with build in SPI. Then it was not friendly to blame questions about it :-( Keep cool. Hi Magnus, for only a single slave I assume, SS can be permanently low. But I have heard, there are some bugs on the 8252 in the slave mode. You should read carefully all Atmel application notes. I see a big problem, if you want to receive 2 or more bytes: The slave transmitter was not buffered. So if the master starts receiving the 2. byte, the slave has no time to put the next byte into the transmit register. Thus the 2. byte was always invalid. The only way to avoid this: The master must wait after every byte, until the slave has handled the SPI (and all others) interrupts and prepared the next byte to transmit. I prefer using the UART. If the UART already in use, I use bit banging in software over 1 or 2 wire. But this depends, how fast data speed was needed. Peter |
| Topic | Author | Date |
| Multipple processord with SPI? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI :) ? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI :) ? | 01/01/70 00:00 | |
| RE: Multipple processord with SPI :) ? | 01/01/70 00:00 | |
RE: Multipple processord with SPI? | 01/01/70 00:00 |



